1. Field of the Invention
The present invention relates generally to a semiconductor chip and, more specifically, to a flip-chip having bond pads on the backside of the chip that are electrically coupled to active devices in the chip.
2. Discussion of Related Art
Within the integrated circuit industry there is a continuing effort to increase integrated circuit speed as well as device density. As a result of these efforts, there is a trend towards using flip chip technology when packaging complex high-speed integrated circuits. Flip chip technology is also known as control collapse chip connection (C4) technology. In flip chip technology, the integrated circuit die is flipped upside down. By flipping the integrated circuit die upside down and exposing the backside, wire bonds may be used to provide direct electrical connections from bond pads formed on the die directly to a corresponding set of pads on a package.
In the following discussion reference will be made to a number of drawings. The drawings are provided for descriptive purposes only and are not drawn to scale.
FIG. 1 illustrates a flip chip 102 that is electrically coupled to a PGA (Pin Grid Array) package 110 by solder bumps (or ball bonds) 104. Chip 102 has a top-side surface 108 and a backside surface 107. The active regions (not shown) of the integrated circuit are formed within the top-side surface 108 of the of the semiconductor chip 102. Because the contact pads of integrated circuit device 102 are located on the top-side surface 108 of the device, the die must be flipped upside down so that it may be attached to package 110.
Today, the trend is toward more complex semiconductor chips having diminished circuit feature sizes and more power, ground and signal contacts. Since the size of the chip is being held at essentially the same size, there has been a movement toward the development of "fine pitch" interconnect technology and circuit board technology which results in more complex and higher cost circuit boards and packages. In addition, with increasing bus frequencies and lowering "on die" voltages, the ability to adequately and efficiently distribute power on the chip is growing increasingly difficult.